Medical Instrumentation
Zahra-Sadat Fatemi; Mohammad Mahdi Ahmadi
Volume 12, Issue 3 , November 2018, , Pages 221-234
Abstract
The use of smart medical implants to study the human brain and the interaction of neurons with each other has recently gained much attention. These implants contain microelectrode arrays in which the size of an electrode is in the order of the size of a neuron; therefore they allow recording signals ...
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The use of smart medical implants to study the human brain and the interaction of neurons with each other has recently gained much attention. These implants contain microelectrode arrays in which the size of an electrode is in the order of the size of a neuron; therefore they allow recording signals from single neuron or stimulating a single neuron with considerable precision. Design of such implants entails many challenges, one of which is the design of power and data recovery blocks. In this paper, we describe the design of a new power and data recovery unit for an implantable neural stimulating microsystem. The power recovery unit generates two supply voltages: a 1.8-V supply for the core circuits and a higher supply voltage for the stimulation front-end. An active rectifier is used to generate the 1.8-V supply. The active rectifier achives a 89% power conversion efficiency and 150mV voltage drop with a 3-V sinusoidal input voltage. In order to maximize the efficiency of the stimulation front-end, the supply voltage of that circuit should be adaptively adjusted according to the amplitude of the stimulation current. As a result, a phase-controlled active rectifier is utilized to generate the supply voltage for the neural stimulation front-end. The phase-controlled active rectifier can generate out voltages ranging from 1.8V to 2.5V. Using phase-controlled active rectifier can increase the power conversion efficiency up to 50%. In addition to power recovery, neuroelectrical stimulation microsystems should receive stimulation data from outside of the body. Hence, this paper also circuits required for clock and daterecovery. The data recovery block is able to demodulate the ASK-modulated signal with 3-V to 5-V amplitude and 5% to 25% modulation index.
Medical Instrumentation
Farnaz Fahimi Hanzaee; Mohammad Mehdi Ahmadi
Volume 12, Issue 2 , September 2018, , Pages 147-159
Abstract
Nowadays, implantable electrical neural stimulation is extensively used to treat or alleviate certain brain-related health conditions, such as in deep brain stimulation (DBS) or in vagus nerve stimulation (VNS). In this paper, we present a digital controller block, designed for a neuroelectrical stimulator ...
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Nowadays, implantable electrical neural stimulation is extensively used to treat or alleviate certain brain-related health conditions, such as in deep brain stimulation (DBS) or in vagus nerve stimulation (VNS). In this paper, we present a digital controller block, designed for a neuroelectrical stimulator chip dedicated for a brain implant.The presented design is very power and area-efficient and provides a great flexibibity in programming the specifications of the stimulation pulses. The duration of each stimulation pulse can programmed to be from 4 µs to 4 ms, and the amplitude of each pulse could be from 4 µA to 1 mA. The stimulation pulses could be either monophasic or biphasic, In addition, in biphasic stimulation, the priority of the cathodic pulse over the anodic pulse, or vice versa, could be pragrammed. The interphase delay between the anodic and cathodic phases could be programmed to be between 4 µs and 512 µs. The controller controls 16 stimulation sites, four of which can be stimulated simoultaneualy. The 16 stimulation sites are divided into four groups, each of which is stimulated by a current-controlled stimulation circuit. Each stimulation circuit is controlled by a local digital controller (LDC), which receives its data from a global digital controller (GDC). The designed controller blocks have been implemented and tested on a Spartan-6 field-programmable gate array (FPGA) board, before being implemented as an application-specific integrated circuit (ASIC) layout. The ASIC circuit has been designed using 0.18-µm CMOS technology. Based on the layout, each LDC occupies an area of 19,160 µm2 and consumes 12 µW of power from a 1.8V supply. On the other hand, the GDC takes up an area of 4,246 µm2 and consumes 8.2 µW of power. We have also created a graphical user interface (GUI) to be able to program the stinulation chip.
